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[VHDL-FPGA-Verilog] fpga-jianpan-ip-core

Description: 基于fpga的键盘设计ip核的vhdl源代码-Ip fpga design of the keyboard based on the vhdl source code for nuclear
Platform: | Size: 4096 | Author: 周勇 | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

[ARM-PowerPC-ColdFire-MIPS] ARM-Verilog-HDL-IP-CORE

Description: ARM Verilog HDL IP CORE
Platform: | Size: 67584 | Author: hebin | Hits:

[VHDL-FPGA-Verilog] fft_ug

Description: altera的FFT IP核的用户手册，介绍了如何使用ALTERA IP核生成FFT核，如何设置参数并讲述了如何仿真，适用于通信方面的FPGA设计工程师，学生。-altera' s FFT IP core user manual describes how to use the ALTERA IP core generated FFT core, how to set parameters and describes how to simulate, for communications, FPGA design engineers, students.
Platform: | Size: 1035264 | Author: zhangdong | Hits:

[VHDL-FPGA-Verilog] vga-ip-core

Description: vga ip core 资料 说明如定制一个ip核-vga ip core information such as a custom ip core
Platform: | Size: 4342784 | Author: shubiao | Hits:

[DSP program] 1553B-bus-protocol-IP-core-design

Description:
Platform: | Size: 130048 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] FFT-module

Description: IP CORE ：FFT模块使用方法，内含源代码，希望对大家有帮助。-IP CORE: FFT module use, including source code, we want to help.
Platform: | Size: 1132544 | Author: haby | Hits:

[VHDL-FPGA-Verilog] Quartus-IP-ram

Description: Quartus IP核的使用方法和处理方法，里面介绍的很详细讲的是IP核的的设计方法。-Quartus IP core using the method and approach, which describes in great detail about the IP core design approach.
Platform: | Size: 681984 | Author: lanqiqing | Hits:

[Program doc] Basic-Multipath-Fading-Channel-Simulator-IP-Core.

Description: Basic Multipath Fading Channel Simulator IP Core
Platform: | Size: 435200 | Author: abc | Hits:

[VHDL-FPGA-Verilog] ram_fifo_ram

Description: 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
Platform: | Size: 8185856 | Author: 袁官福 | Hits:

[VHDL-FPGA-Verilog] dma_0

Description: SOPC系统编译的DMA的Verilog代码-DMA IP core in SOPC
Platform: | Size: 5120 | Author: zy | Hits:

[Other] ise-ip-core

Description: IP核包括硬IP与软IP。调用IP核能避免重复劳动，大大减轻设计人员的工作量。-IP cores, including hard IP and soft IP. IP calls to avoid duplication of nuclear energy, thus greatly reducing the workload of the designer.
Platform: | Size: 352256 | Author: zfj | Hits:

[VHDL-FPGA-Verilog] FIFOED_UART

Description: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Platform: | Size: 6144 | Author: 杨胜尧 | Hits:

[VHDL-FPGA-Verilog] FFT-IP-CORE--of-Quartus

Description: Quartus中fft ip core的使用一点心得，希望对大家有所帮助。-The Quartus fft the ip core to use a little experience, we hope to help.
Platform: | Size: 313344 | Author: lg | Hits:

[VHDL-FPGA-Verilog] the-use-of-Quartus-and-IP-core

Description: QuartusIP核的使用,很适合初学者使用-the use of Quartus and IP core
Platform: | Size: 681984 | Author: xingyewuyu | Hits:

[VHDL-FPGA-Verilog] Intel8086-IP-core

Description: intel 8086 cpu IP core.
Platform: | Size: 252928 | Author: jerryzhang | Hits:

[Other] AES-IP-core-key-expansion-module

Description: AES IP核密钥扩展模块设计与仿真（设计过程及程序，测试程序）-AES IP core key expansion module design and simulation (the design process and procedures, test procedures)
Platform: | Size: 39936 | Author: 周涛 | Hits:

[Other] AES--IP-core-architecture-design

Description: AES算法分析及其IP核体系结构设计（包括设计过程及代码）-AES algorithm analysis and its IP core architecture design
Platform: | Size: 165888 | Author: 周涛 | Hits:

[Other] AES-IP-core-encryption-module-design

Description: AES IP核加密模块的设计与仿真(包括设计过程及代码)- the AES IP core encryption module design and simulation
Platform: | Size: 76800 | Author: 周涛 | Hits:

[Other] AES-IP-core-control-module-design

Description: AES IP核的控制模块的设计与仿真以及系统集成与仿真-AES IP core design and simulation of the control module and system integration and simulation
Platform: | Size: 59392 | Author: 周涛 | Hits:
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